PDF《Simultaneous Read/Write Flash》

when low during burst mode, causes starting address to be latched at the next active clock edge. When high, device ignores address inputs. RESET# Input Hardware Reset. Low = device resets and returns to reading array data. WP# Input Write Protect. At VIL, disables program and erase functions in the four outermost sectors. Should be at VIH for all other conditions. ACC Input Acceleration Input. At VHH, accelerates programming;

automatically places device in unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions. RFU Reserved Reserved for future use (see MCP look-ahead pinout for use with MCP). Document Number: 002-01747 Rev. *A Page

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86 S29WS512P S29WS256P S29WS128P 3. Block Diagrams Notes: 1. AMAX-A0 = A24-A0 for the WS512P, A23-A0 for the WS256P, and A22-A0 for the WS128P. 2. n =

15 for WS512P / WS256P / WS128P. 4. Physical Dimensions/Connection Diagrams This section shows the I/O designations and package specifications for the S29WS-P. 4.1 Related Documents The following documents contain information relating to the S29WS-P devices. Click on the title or go to www.spansion.com to download the PDF file, or request a copy from your sales office. ? Considerations for X-ray Inspection of Surface-Mounted Flash Integrated Circuits 4.2 Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. VSS VCC Bank Address RESET# ACC WE# CEx# AVD# RDY DQ15CDQ0 WP# STATE CONTROL &

COMMAND REGISTER Bank

1 X-Decoder Y-Decoder Latches and Control Logic Bank

0 X-Decoder Y-Decoder Latches and Control Logic DQ15CDQ0 DQ15CDQ0 DQ15CDQ0 DQ15CDQ0 DQ15CDQ0 Bank (n-1) Y-Decoder X-Decoder Latches and Control Logic Bank (n) Y-Decoder X-Decoder Latches and Control Logic OE# Status Control AMAXCA0 AMAXCA0 AMAXCA0 AMAXCA0 Bank Address Bank Address Bank Address VCCQ Document Number: 002-01747 Rev. *A Page

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86 S29WS512P S29WS256P S29WS128P Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. Figure 4.1 84-Ball Fine-Pitch Ball Grid Array, 512,

256 &

128 Mb Notes: 1. Balls F6 and G8 are RFU on the WS128P. 2. Ball G8 is RFU on the WS256P. 3. VCC pins must ramp simultaneously. H4 H5 H6 H7 H8 H2 G7 G8 G9 F7 F8 F9 E7 E8 E9 D7 D8 D9 C5 H2 H2 C6 C7 F-CE# H3 OE# RFU DQ0 C2 C3 B2 B3 AVD# VSS WP# A7 A8 WE# ACC RFU B4 B5 B6 B7 C8 C9 RFU A11 B8 B9 RFU RFU RFU VCC RFU CLK A15 A12 A19 A21 A13 A9 A22 A14 A10 A16 A24 DQ6 G6 F6 E6 RFU A20 A23 RFU G4 G5 F4 F5 E4 E5 D5 RESET# RFU RDY A18 RFU A17 RFU DQ1 RFU DQ15 DQ13 DQ4 DQ3 DQ9 DQ7 RFU VCC DQ10 G2 G3 F2 F3 E2 E3 D2 D3 A6 A3 A5 A2 A4 A1 VSS A0 L2 L3 RFU DQ8 RFU RFU VSS DQ12 RFU DQ14 DQ5 RFU DQ11 DQ2 L4 L5 L6 L7 L8 L9 VCCQ RFU RFU VCC VSS A1 NC A10 NC RFU M10 NC M1 NC H2 C4 D4 D6 Reserved for Future Use Do Not Use Ground J4 J5 J6 J7 J8 J9 J2 J3 K2 K3 K4 K5 K6 K7 K8 K9 Power Legend (Top View, Balls Facing Down, MCP Compatible) Document Number: 002-01747 Rev. *A Page

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86 S29WS512P S29WS256P S29WS128P Figure 4.2 VBH084―84-ball Fine-Pitch Ball Grid Array, 11.6 x

8 mm MCP Compatible Package Note: BSC is an ANSI standard for Basic Space Centering. 4.3 MCP Look-ahead Connection Diagram Spansion Inc. provides this standard look-ahead connection diagram that supports ? NOR Flash and SRAM densities up to

4 Gigabits ? NOR Flash and pSRAM densities up to

4 Gigabits ? NOR Flash and pSRAM and data storage densities up to