PDF《ZHCSEW6E – MAY 2013 – REVISED》

17 8.3 Feature Description.18 8.4 Device Functional Modes.21 8.5 Programming

26 8.6 Register Maps.30

9 Application and Implementation

37 9.1 Application Information.37 9.2 Typical Applications

39 10 Power Supply Recommendations

43 11 Layout.44 11.1 Layout Guidelines

44 11.2 Layout Example

45 12 器 器件 件和 和文 文档 档支 支持 持47 12.1 文档支持.47 12.2 接收文档更新通知

47 12.3 社区资源.47 12.4 商标.47 12.5 静电放电警告.47 12.6 术语表

47 13 机 机械 械、 、封 封装 装和 和可 可订 订购 购信 信息 息.47

4 修 修订 订历 历史 史记 记录 录Changes from Revision D (October 2016) to Revision E Page ? Added recommendation to ensure GPO2 is low when PDB goes high

6 ? Added Power Over Coax supply noise to the recommended operating conditions table

8 ? Clarified PCLK clock frequency range and added external clock input frequency range

8 ? Added strap pin input current specification for MODE and IDX pins

9 ? Updated TJIT1 PCLK input jitter in the external oscillator mode

11 ? Added clarification on MODE pin description in PCLK from imager mode

22 ? Updated pullup and pulldown resistor to R1 and R2 in MODE pin configuration diagram

22 ? Updated the MODE setting values to ratio.23 ? Updated pullup and pulldown resistor for IDX to R3 and R4 in the diagram.28 ? Updated IDX setting values to ratio

28 ? Updated register TYPE column per legend

30 ? Added type and default value to the reserved register bits that were missing this information

30 ? Added that register 0x00[7:1] does not auto update IDX strapped address

30 ? Added description for 0x05 bits

1 and

0 (TX_MODE_12b and TX_MODE_10b)32 ? Clarified description on PDB pin usage during power up

37 ? Added paragraph to explain setting registers if GPO2 state is not determined when PDB goes high

37 ? Added GPO2 to suggested power-up sequencing diagram

37 ? Added timing constraint for PDB to GPO2 delay

38 ? Revised coax connection diagram to include pulldown resistor for GPO2

40 ? Revised STP connection diagram to include pulldown resistor for GPO2

42 3 DS90UB913A-Q1 www.ti.com.cn ZHCSEW6E CMAY 2013CREVISED SEPTEMBER

2018 版权 ? 2013C2018, Texas Instruments Incorporated Changes from Revision C (April 2016) to Revision D Page ? Added back channel line rate = 5.5 MHz as test condition;

also added footnote for clarification between MHz and Mbps distinction.10 ? Removed '

ns'

unit from specifications referencing period in units of T.11 ? Updated test condition specs for jitter bandwidth regarding tJIT0, tJIT1, and tJIT2.11 ? Added input external oscillator frequency range for pin/freq.11 ? Added parameter for typical external oscillator frequency stability.11 ? Added test conditions to tJIND, tJINR, and tJINT.15 ? Added DOUT± as measured output pins for jitter parameters.15 ? Added note (6) for Serializer output peak-to-peak total jitter includes deterministic jitter, random jitter, and jitter transfer from serializer input

15 ? Added jitter tolerance curve for typical system IJT configuration with DS90UB913A linked to DS90UB914A.16 ? Added device functional mode table for external oscillator operation with example XCLKIN = 48MHz.21 ? Revised rise time and delay conditions to include 10% to 90% parameters instead of VIH and VIL.38 ? Changed max rise time for VDDIO and VDD_N to be 5ms instead of 1.5ms during power-up.38 Changes from Revision B (December 2014) to Revision C Page ? 将文档拆分成两个单独的文档(部件 DS90UB913A-Q1 和DS90UB914A-Q1)1 ? 已修改汽车 特性