PDF《ZHCSEW6E – MAY 2013 – REVISED》

1 ? Updated pin description for DIN to include active/inactive outputs corresponding to MODE setting.5 ? Added pin description to GPO pins to leave open if unused.6 ? Changed Air Discharge ESD Rating (IEC61000-4-2: RD =

330 ?, CS =

150 pF) to minimum ±25000 V.7 ? Added RTV text to Thermal Information table.8 ? Added GPO[3:0] typical pin capacitances.9 ? Changed Differential Output Voltage minimum specification.9 ? Changed Single-Ended Output Voltage minimum specification.9 ? Added Back Channel Differential Input Voltage minimum specification.10 ? Added Back Channel Single-Ended Input Voltage minimum specification.10 ? Updated IDDT for VDD_n=1.89V, VDDIO=3.6V, RL=100?, Random Pattern with f=100 MHz, 10-bit mode to typical value of

65 mA;

value is currently

54 mA.10 ? Updated IDDT for VDD_n=1.89V, VDDIO=3.6V, RL=100?, Random Pattern with f=75 MHz, 12-bit high freq mode to typical value of

64 mA;

value is currently

54 mA.10 ? Updated IDDT for VDD_n=1.89V, VDDIO=3.6V, RL=100?, Random Pattern with f=50 MHz, 12-bit low freq mode to typical value of

63 mA;

value is currently

54 mA.10 ? Updated frequency ranges for MODE settings and also revised with correct maximum clock periods. Added footnote and nominal clock period to be in terms of '

T'

.(5)

11 ? Deleted Revised jitter freq. test conditions to be >

f/20 and also updated typical values for tjit0and tjit2.11 ? Updated VOL Output Low Level row with revised IOL currents and max VOL voltages, dependent upon VDDIO voltage.12 ? Updated Figure

2 title to state '

Worst-Case Test Pattern for Power Consumption'

13 ? Added footnote that states the following: UI C Unit Interval is equivalent to one serialized data bit width. The UI scales with PCLK frequency. Add below calculations to footnote. 12-bit LF mode

1 UI =

1 / ( PCLK_Freq. x

28 ) 12- bit HF mode

1 UI =

1 / ( PCLK_Freq. x 2/3 x

28 ) 10-bit mode

1 UI =

1 / ( PCLK_Freq. /2 x

28 15 ? Updated frequency requirements for 10-bit and 12-bit HF modes. 10-bit mode C

50 MHz to

100 MHz;

12-bit HF mode C 37.5 MHz to

75 MHz;

12-bit LF mode (no change) C

25 MHz to

50 MHz.17 ? Updated register 0x01[1] default value to be

0 30 ? Changed GPO0 Enable for 0x0D[4] to GPO1 Enable.33 ? Added Inject Forward Channel Error Register 0x2D.36

4 DS90UB913A-Q1 ZHCSEW6E CMAY 2013CREVISED SEPTEMBER

2018 www.ti.com.cn Copyright ? 2013C2018, Texas Instruments Incorporated ? Updated power up sequencing information and timing diagram.37 ? Added ........