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1 IXYS reserves the right to change limits, test conditions and dimensions Contents Page Symbols and Definitions

2 Nomenclature

2 General Informations for Chips

3 Assembly Instructions

4 FRED, Rectifier Diode and Thyristor Chips in Planar Design

5 IGBT Chips VCES IC G-Series, Low VCE(sat) B2 Types

600 .

..1200 V

7 ...

20 A

6 G-Series, Fast C2 Types

600 V

7 ...

20 A

6 S-Series, SCSOA Capability, Fast Types

600 V

10 ...

20 A

6 E-Series, Improved NPT? technology

1200 ...

1700 V

20 ...

150 A

7 MOSFET Chips VDSS RDS(on) HiPerFETTM Power MOSFET

70 ...1200 V 0.005 ... 4.5 ? 8-10 PolarHT/HVTM Power MOSFET

55 ...

600 V 0.015 ... 0.135 ?

11 PolarHT/HVTM HiPerFET Power MOSFET

100 ...

600 V 0.0075 ... 0.74 ? 12-14 N-Channel Depletion Mode MOSFET

500 ...1000 V

30 ...

110 ?

15 P-Channel Power MOSFET -100 ...-600 V 0.06 ... 1.2 ?

15 Chip outlines 16-23 Bipolar Chips VRRM / VDRM IF(AV)M / IT(AV)M RectifierDiodes

800 ...

2200 V

12 ...

788 A 24-25 FREDs

200 ...

1200 V

8 ...

244 A 26-28 LowLeakageFREDs

200 ...

1200 V

9 ...

148 A 29-30 SONIC-FRDTM Diodes

600 ...

1800 V

12 ...

150 A 31-32 GaAsSchottkyDiodes

100 ...

300 V 3.5 ...

25 A 33-34 SchottkyDiodes

8 ...

200 V

28 ...

145 A 35-38 PhaseControlThyristors

800 ...

2200 V

15 ...

540 A 39-40 FastRectifierDiodes

1600 ...

1800 V

10 ...

26 A

41 Direct Copper Bonded (DCB) Ceramic Substrates What is DCB?

42 DCB Specification

43 www.ixys.com

2 ?

2008 IXYS All rights reserved RegistrationNo.: OHSAS18001: 001947OH Symbols and Definitions Cies Input capacitance of IGBT Ciss Input capacitance of MOSFET -di/dt Rate of decrease of forward current IC DC collector current ID Drain current IF Forward current of diode IF(AV)M Maximum average forward current at specified Th IFSM Peak one cycle surge forward current IGT Gate trigger current IR Reverse current IRM Maximum peak recovery current IT Forward current of thyristor IT(AV)M Maximum average on-state current of a thyristor at specified Th ITSM Maximum surge current of a thyristor RDS(on) Static drain-source on-state resistance Rthjc Thermal resistance junction to case rT Slope resistance of a thyristor or diode (for power loss calculations) Tcase Case temperature Th Heatsink temperature tfi Current fall time with inductive load Tj , T(vj) Junction temperature Tjm , T(vj)m Maximum junction temperature trr Reverse recovery time of a diode VCE(sat) Collector-emitter saturation voltage VCES Maximum collector-emitter voltage VDRM Maximum repetitive forward blocking voltage of thyristor VDSS Drain-source break-down voltage VF Forward voltage of diode VR Reverse voltage VRRM Maximum peak reverse voltage of thyristor or diode VT On-state voltage of thyristor VT0 Threshold voltage of thyristors or diodes (for power loss calculation only) Chip and DCB Ceramic Substrates catalogue Edition

2008 Published by IXYS Semiconductor GmbH Marketing Communications Edisonstra?e 15, D-68623 Lampertheim ? IXYS Semiconductor GmbH All Rights reserved As far as patents or other rights of third parties are concerned, liability is only assumed for chips and DCB parts per se, not for applications, processes and circuits implemented with components or assemblies. Terms of delivery and the right to change design or specifications are reserved. Nomenclature IGBT and MOSFET Discrete IXSD 40N60A (Example) IX IXYS Die technology E NPT3 IGBT F HiPerFETTM Power MOSFET G Fast IGBT S IGBT with SCSOA capability T Standard Power MOSFET D Unassembled chip (die)

40 Current rating,

40 =

40 A N N-channel type P P-channel type

60 Voltage class,

60 =

600 V xx MOSFET A Prime RDS(on) for standard MOSFET Q Low gate charge die Q2 Low gate charge die, 2nd generation P PolarHT/HV Power MOSFET L Linear Mode MOSFET IGBT -- No letter, low VCE(sat) A Or A2, std speed type B Or B2, high speed type C Or C2, very high speed type W-CWP 55-12/18 (Thyristor Example) W Package type C Chip function C = Silicon phase control thyristor W Unassembled chip P Process designator P = Planar passivated chip cathode on top

55 Current rating value of one chip in A 12/18 Voltage class, 12/18 =

1200 up to

1800 V Diode and Thyristor Chips C-DWEP 69-12 (Diode Example) C Package type D Chip function D = Silicon rectifier diode W Unassembled chip EP Process designator EP = Epitaxial rectifier diode N = Rectifier diode, cathode on top P = Rectifier diode, anode on top FN = Fast Rectifier diode, cathode on top FP = Fast Rectifier diode, anode on top

69 Current rating value of one chip in A -12 Voltage class,

12 =

1200 V RegistrationNo.: ISO/TS16949: 001947TS2 RegistrationNo.: ISO14001: 001947UM

3 IXYS reserves the right to change limits, test conditions and dimensions General Informations for Chips When mounting Power Semiconductor chips to a header, ceramic substrate or hybrid thick film circuit, the solder system and the chip attach process are very important to the reliability and performance of the final product. This brochure provides several guidelines that describe recommended chip attachment procedures. These methods have been used successfully for many years at IXYS. Available Packaging Options IXYS offers various options. Please order from one of the following possibilities: Packaging Options Delivery form C-...* Chips in tray (Waffle Pack);

Electrically tested T-...* Chips in wafer, unsawed;

Bipolar =

5 (125 mm?) wafer;

or

6 (150 mm?) W-...* Chips in wafer on foil, sawed;

Bipolar =

5 (125 mm?) wafer;

or

6 (150 mm?) ...* must be amended by the exact chip type designation. Package, Storage and Handling Chips should be transported in their original containers. All chip transfer to other containers or for assembly should be done only with rubber-tipped vacuum pencils. Contact with human skin (or with a tool that has been touched by hand) leaves an oily residue that may adversely impact subsequent chip attach or reliability. At temperatures below 104°F (40°C), there is no limitation on storage time for chips in sealed original packages. Chips removed from original packages should be assembled immediately. The wetting ability of the contact metallization with solder can be preserved by storage in a clean and dry nitrogen atmosphere. The IGBT and MOSFET Chips are electrostatic discharge (ESD) sensitive. Normal ESD precautions for handling must be observed. Prior to chip attach, all testing and handling of the chips must be done at ESD safe work stations according to DIN IEC 47(CO) 701. Ionized air blowers are recommended for added ESD protection. Contamination of the chips degrades the assembly results.Finger prints, dust or oily deposits on the surface of the chips have to be absolutely avoided. Rough mechanical treatment can cause damage to the chip. ElectricalTests The electrical properties listed in the data sheet presume correctly assembled chips. Testing of non-assembled chips requires the following precautions: ? High currents have to be supplied homogeneously to the whole metallized contact area. ? Kelvin probes must be used to test voltages at high currents ? Applying the full specified blocking or reverse voltage may cause arcing across the glass passivated junction termination, because the electrical field on top of the passivation glass causes ionization of the surrounding air. This phenomenon can be avoided by using inert fluids or by increasing the pressure of the gas surrounding the chip to values above

30 psig (2 bars). General Rules for Assembly The linear thermal expansion coefficient of silicon is very small compared to usual contact metals. If a large area metallized silicon chipisdirectlysolderedtoametallikecopper,enormous shear stress is caused by temperature changes (e.g. when cooling down from the solder temperature or by heating during working conditions) which can disrupt the solder mountdown. If it is found that larger chips are cracking during mountdown or in the application, then the use of a low thermal expansion coefficient buffer layer,e.g. tungsten,molybdenum or Trimetal? , for strain relief should be considered. An alternative solution is to soft-solder these larger chips to DCB ceramic substrates because of their matching thermal expansion coefficients. Electrically tested, rejects are inked Electrically test........