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31 32 (OC2/OC1C) PB7 TOSC2/PG3 TOSC1/PG4 RESET VCC GND XTAL2 XTAL1 (SCL/INT0) PD0 (SDA/INT1) PD1 (RXD1/INT2) PD2 (TXD1/INT3) PD3 (ICP1) PD4 (XCK1) PD5 (T1) PD6 (T2) PD7 AVCC GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC PA0 (AD0) PA1 (AD1) PA2 (AD2)

3 ATmega128 2467OSCAVRC10/06 Block Diagram Figure 2. Block Diagram PROGRAM COUNTER INTERNAL OSCILLATOR WATCHDOG TIMER STACK POINTER PROGRAM FLASH MCU CONTROL REGISTER SRAM GENERAL PURPOSE REGISTERS INSTRUCTION REGISTER TIMER/ COUNTERS INSTRUCTION DECODER DATA DIR. REG. PORTB DATA DIR. REG. PORTE DATA DIR. REG. PORTA DATA DIR. REG. PORTD DATA REGISTER PORTB DATA REGISTER PORTE DATA REGISTER PORTA DATA REGISTER PORTD TIMING AND CONTROL OSCILLATOR OSCILLATOR INTERRUPT UNIT EEPROM SPI USART0 STATUS REGISTER Z Y X ALU PORTB DRIVERS PORTE DRIVERS PORTA DRIVERS PORTF DRIVERS PORTD DRIVERS PORTC DRIVERS PB0 - PB7 PE0 - PE7 PA0 - PA7 PF0 - PF7 RESET VCC AGND GND AREF XTAL1 XTAL2 CONTROL LINES + - ANALOG COMPARATOR PC0 - PC7 8-BIT DATA BUS AVCC USART1 CALIB. OSC DATA DIR. REG. PORTC DATA REGISTER PORTC ON-CHIP DEBUG JTAG TAP PROGRAMMING LOGIC PEN BOUNDARY- SCAN DATA DIR. REG. PORTF DATA REGISTER PORTF ADC PD0 - PD7 DATA DIR. REG. PORTG DATA REG. PORTG PORTG DRIVERS PG0 - PG4 TWO-WIRE SERIAL INTERFACE

4 ATmega128 2467OSCAVRC10/06 The AVR core combines a rich instruction set with

32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega128 provides the following........