PDF《DRV8313 三个半 H 桥驱动器集成电路 （IC）》

2012 PIN DESCRIPTIONS PIN TYPE DESCRIPTION EXTERNAL COMPONENTS OR CONNECTIONS NAME NO. Power and Ground CP1

1 IO Charge-pump flying capacitor Connect a 0.01-μF 100-V capacitor between CP1 and CP2. CP2

2 IO Charge-pump flying capacitor 12, 20, 28, GND C Device ground Connect to system ground PPAD Bypass to GND with a 0.47-μF 6.3-V ceramic capacitor. Use V3P3OUT

15 O 3.3-V regulator output for suppling external loads is permissible. VCP

3 IO High-side gate drive voltage Connect a 0.1-μF 16-V ceramic capacitor to VM. Connect to power supply (8.2 VC60 V). Connect both pins to VM 4,

11 C Main power supply the same supply. Bypass to GND with a 10-?F (minimum) capacitor. Control EN1

26 I Channel

1 enable Logic high enables OUT1. Internal pulldown EN2

24 I Channel

2 enable Logic high enables OUT2. Internal pulldown EN3

22 I Channel

3 enable Logic high enables OUT3. Internal pulldown IN1

27 I Channel

1 input Logic input controls state of OUT1. Internal pulldown IN2

25 I Channel

2 input Logic input controls state of OUT2. Internal pulldown IN3

23 I Channel

3 input Logic input controls state of OUT3. Internal pulldown Active-low reset input initializes internal logic and disables the nRESET

16 I Reset input outputs. Internal pulldown Logic high to enable device, logic low to enter low-power sleep nSLEEP

17 I Sleep-mode input mode. Internal pulldown Status Logic low when in fault condition (overtemperature, nFAULT

18 OD Fault overcurrent, UVLO) Comparator COMPN

13 I Comparator negative input Negative input of comparator COMPP

12 I Comparator positive input Positive input of comparator nCOMPO

19 OD Comparator out Output of comparator. Open-drain output Copyright ? 2012, Texas Instruments Incorporated

3 DRV8313 ZHCSAD6A COCTOBER 2012CREVISED NOVEMBER

2012 www.ti.com.cn PIN DESCRIPTIONS (continued) PIN TYPE DESCRIPTION EXTERNAL COMPONENTS OR CONNECTIONS NAME NO. Output OUT1

5 O Output

1 OUT2

8 O Output

2 Connect to loads. OUT3

9 O Output

3 PGND1

6 C Ground for OUT1 PGND2

7 C Ground for OUT2 Connect to ground, or to low-side current-sense resistors. PGND3

10 C Ground for OUT3 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted)(1)(2) VALUE UNIT Power-supply voltage range (VM) C0.3 V to

65 V Digital-pin voltage range C0.5 to

7 V Comparator input-voltage range C0.5 to

7 V Peak motor-drive output current Internally limited A Pin voltage (GND1, GND2, GND3) ±600 mV Continuous motor-drive output current(3) 2.5 A TJ Operating virtual junction temperature range C40 to

150 ?C Tstg Storage temperature range C60 to

150 ?C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to the network ground terminal. (3) Observe power dissipation and thermal limits. THERMAL INFORMATION DRV8313 THERMAL METRIC(1) PWP UNIT

28 PINS θJA Junction-to-ambient thermal resistance(2) 31.6 °C/W θJCtop Junction-to-case (top) thermal resistance(3) 15.9 °C/W θJB Junction-to-board thermal resistance(4) 5.6 °C/W ψJT Junction-to-top characterization parameter(5) 0.2 °C/W ψJB Junction-to-board characterization parameter(6) 5.5 °C/W θJCbot Junction-to-case (bottom) thermal resistance(7) 1.4 °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections