PDF《APPLICATION NOTE》

A/D Range Control Using the ISL5416 3G QPDC APPLICATION NOTE AN1017 Rev 0.

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27 May

2002 AN1017 Rev 0.00 May

2002 Overview: The ISL5416 has a range control circuit that monitors the samples from the A/D and adjusts the RF/IF gain to optimize receiver sensitivity. The circuit reduces gain when large signals are present to prevent A/D saturation and increases gain to maximize sensitivity when no large signals are present. This shifts the instantaneous dynamic range of the A/D up and down within the total receiver range set by A/D dynamic range plus the RF/IF attenuation. The RF/IF attenuation controlled by the range control circuit can be thought of as the exponent portion of a floating-point digitizer and the A/D output thought of as the mantissa. The ISL5416 requires that the gain adjustments be in

6 dB increments though in general, floating-point digitizers can use any exponent step size. The DSP processing in the ISL5416 adds

6 dB of gain to the A/D output (mantissa) for each

6 dB of RF/IF attenuation step. This converts the floating-point samples to fixed point for processing. The overall gain is constant through the RF, A/D, and DSP front end. A simplified block diagram is provided in figure 1. Figure

2 illustrates what happens to the signal at various points from the RF to through the DSP front end. As the RF signal level increases, the signal envelope at the A/D output crosses a threshold and the range control circuit increases the RF attenuation to reduce the signal level at the A/D input. Whenever the RF attenuation is increased, the DSP gain is increased to compensate and maintain a constant overall gain from the RF through the DSP front end. The attenuation and gain controls signals are in offset in time to compensate for the delays from the RF through the A/D and DSP. Figure

3 illustrates how the instantaneous dynamic range of the A/D maps to the RF signal range. As attenuation is added, the full scale at the A/D corresponds to a larger RF signal power. The added attenuation, however, also raises the A/D noise floor relative to the RF input and reduces sensitivity. ~ ~ ~ CABLE, F1 G = -2 dB ATTEN

6 dB Steps A/D LNA LEVE L DETECTORS MAP Z - N EXPONENT MANTISSA ATTEN CODE FILTER GROUP DELAY A/D PIPELINE DELAYS Z -

4 ISL5416 PIPELINE DELAYS ATTENUATOR SETTLING TIME + + + = COMPENSATING DELAY Z -2 Z -

2 ISL5416 NOTE: The compensating delay, Z - N , is chosen as close as possible to the sum of the settling time, group delay, and pipeline delays. This minimizes the transient due to an attenuation change. The delay is programmable from

1 to

256 clock periods (12 ns to 3.2 us at

80 MSPS). FIGURE 1. TYPICAL SYSTEM CONFIGURATION, INCLUDING SIGNAL DELAYS A/D Range Control Using the ISL5416 3G QPDC AN1017 Rev 0.00 Page

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27 May

2002 RF A/D OUTPUT

1 - DETECTOR THRESHOLD

2 - RF, A/D DELAY

3 - RANGE CONTROL DELAY

4 - ISL5416 INPUT DELAY SHIFTER OUTPUT ISL5416 RANGE CONTROL WAVEFORMS

2 3

4 1 RF ATTEN OUTPUT SHIFT CONTROL x

1 x

2 x

4 0 dB

6 dB

12 dB

2 4

4 RF ATTEN CONTROL

3 FIGURE 2. ISL5416 RANGE CONTROL WAVE FORMS FIGURE 3. MAPPING THE RF INPUT TO THE A/D RANGE MA PPING THE RF INPUT TO THE A/D RANGE -14 -20 -26 -32 -38 -44 -50 -56 -62 -68 -74 -80 -86 -92 -98 -

104 -

110 -

116 -

122 -

128 -

134 -

6 dBFS

0 -

12 -

18 -

24 -

30 -

36 -

42 -

48 -

54 -

60 -

66 -

72 -

78 -

84 24

18 12

6 0 dB RF ATTENUATION 14b A/D

72 dB SNR @

7 6.8MSPS A/D FULL SCALE (dBm) -