PDF《APPLICATION NOTE》

0 to

42 dB in

6 dB steps. These three bits are routed to the tuner channels that receive the input samples and control the amount of additional gain that is added by a barrel shifter that precedes the CIC filter. The gain is added at the CIC to maximize the dynamic range through the NCO/mixer stage. The three gain control bits are delayed by a programmable delay stage to compensate for the delays in the RF/IF/DSP due to attenuator settling time, filter group delays, and A/D and DSP pipeline delays and align the CIC shifter gain changes with the RF changes. The delay is programmable from

1 to

256 clock periods, providing up to 2.56 usec at

100 MSPS. A/D Range Control Using the ISL5416 3G QPDC AN1017 Rev 0.00 Page

4 of

27 May

2002 FIGURE 4. RANGE CONTROL BLOCK DIAGRAM LUT PROG DE LAY

1 -256 CLO CK S (~3 usec @

80 M) EN INPUT E XP EN A TTE N EX P R EO UT M AP B YP BW SE L E X '

P HPF | X | | X | MANT ? R R BA RREL SHIF T ? ? ? A A A B B B T H1 TH2 T H3 DOW N CNTR R DECODE M U X DE LTA

1 DE LTA

2 DE LTA

3 L EAK

0 ? u P ENA B LE LIM DE T UPP E R GA IN LIMI T M U X R LOWE R GA IN LI MIT 2^ -1 TO -1

6 LD PRLD(7:0) A>

B A>

B A<

B ? SY NC DOW N COUNTER DOW N COUNTER DOW N COUNTER I NT ERVA L (SLOT PE RI OD) DELA Y (SY NC TO ST A RT OF INTE GRA TION) LD EN LD LD EN =0 =

0 HI5828 DAC, ~-5 to -6 dBm full scale ->

10.7M LPF ->

Digital Attenuator,

6 dB steps,

2 dB min attenuation ->

Power divider (-4.5 dB gain) ->

10.7M LPF ->

14bit A/D, ~72 dB SNR, +4 dBm full scale ->

ISL5416 Digital Down-........