PDF《APPLICATION NOTE》

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152 (RF Referred) A/D Range Control Using the ISL5416 3G QPDC AN1017 Rev 0.00 Page

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27 May

2002 The ISL5416 Range Control Operation Description Figure

4 is a simplified system block diagram of the ISL5416 range control circuitry. The input samples from the A/D are monitored with a set of filters and level detectors. The level detector decisions control whether to increase or decrease the contents of an accumulator that holds an RF/IF attenuation word. Only the MSBs of the accumulator are mapped to the attenuation control bits, so by programming the accumulator changes to be below these MSBs, the accumulator can act as a filter on the detector outputs. Programmable upper and lower limits restrict the accumulator to only the attenuation range that is needed. There are two signal paths for the samples from the A/D converter. In one path, the absolute value of each sample is compared to a programmable threshold. In the other path, the samples are averaged before making a decision. In the sample-by-sample path, if any sample exceeds the threshold, the RF/IF attenuation is immediately increased. The purpose of this detector is to prevent saturation of the A/D converter due a rapid increase in input power, and this detector is given the highest priority. The threshold for this detector is usually set within a few dB of the A/D full scale and the gain adjustment from an immediate threshold crossing usually set to 6.02 dB. After an immediate threshold crossing, the immediate detector is disabled for a programmable number of samples to allow the loop to settle before making another adjustment. The other signal path filters the A/D samples before making decisions. The samples are first high-pass filtered to block DC offsets from the A/D converter. The absolute values of the samples are then averaged in an integrate-and-dump circuit. The integration period is programmable from

2 to

65536 samples. Averaging reduces the standard deviation of the samples for a better decision and is a necessity for a lower limit comparison since the A/D samples pass through zero. The integrator output is divided by 2^N in a barrel shifter to compensate for growth in the integrator and reduce the range of the data to the detectors. The average magnitude is next compared against upper and lower thresholds. In the averaged signal path, threshold decisions are only made at the end of the integration period. If the upper threshold is exceeded, the attenuation control accumulator is increased by a programmable amount. If the average falls below the lower threshold, the accumulator is decreased by a separate programmable amount. These average signal thresholds set the desired operating limits for the signal to the A/D. The upper limit is typically set based on the peak-to-average ratio of the expected input signals with sufficient back off to prevent tripping the immediate threshold. The lower limit is set to guarantee a minimum SNR from the RF and/or a minimum number of effective bits from of the A/D converter. When the signal falls below this threshold, attenuation is removed to lower the RF noise figure and to increase the signal to the A/D so that more bits toggle. If the average magnitude is between the upper and lower averaged limits, at the end of the integration period a programmable bias value is added to the attenuation control accumulator. This bias slowly adds or removes attenuation to bias the signal toward one end of the operating range. This bias overcomes the large hysteresis that results when there is a large separation between the upper and lower thresholds. For small separations between the upper and lower thresholds, the bias can be disabled. The three MSBs of the attenuation control accumulator represent the attenuation value from