PDF《BLF7G20L-90P; BLF7G20LS-90P》

3 ―

1 September

2015 9 of

15 BLF7G20L-90P;

BLF7G20LS-90P Power LDMOS transistor 7.8 Impedance information Table 9. Typical impedance Typical values valid for both section in parallel unless otherwise specified. f ZS ZL MHz ? ?

1800 1.0 ? j3.3 2.8 ? j2.7

1840 1.2 ? j3.3 2.8 ? j2.5

1880 1.1 ? j3.4 2.7 ? j2.4 Fig 13. Definition of transistor impedance 001aal831 gate drain ZS ZL BLF7G20L-90P_7G20LS-90P#3 All information provided in this document is subject to legal disclaimers. ? Ampleon The Netherlands B.V. 2015. All rights reserved. Product data sheet Rev.

3 ―

1 September

2015 10 of

15 BLF7G20L-90P;

BLF7G20LS-90P Power LDMOS transistor 8. Package outline Fig 14. Package outline SOT1121A References Outline version European projection Issue date IEC JEDEC JEITA SOT1121A 09-10-12 10-02-02 Flanged LDMOST ceramic package;

2 mounting holes;

4 leads SOT1121A E1 Q E c D A F........